A Simulation Study of Decoupled Architecture Computers
IEEE Transactions on Computers
Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
Optimal pipelining in supercomputers
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Checkpoint repair for out-of-order execution machines
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
The performance potential of multiple functional unit processors
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
The TI Advanced Scientific Computer
Computer
I-NET mechanism for issuing multiple instructions
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
A sequencing-based taxonomy of I/0 systems and review of historical machines
ACM SIGARCH Computer Architecture News
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
Quick and easy cache performance analysis
ACM SIGARCH Computer Architecture News
The Evolution of Instruction Sequencing
Computer - Special issue on instruction sequencing
IEEE Annals of the History of Computing
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Classification and performance evaluation of instruction buffering techniques
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
OHMEGA: a VLSI superscalar processor architecture for numerical applications
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Strategies for achieving improved processor throughput
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Comparing static and dynamic code scheduling for multiple-instruction-issue processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Time multiplexed optical computers
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Distributed Instruction Set Computer Architecture
IEEE Transactions on Computers
Improving instruction supply efficiency in superscalar architectures using instruction trace buffers
SAC '92 Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990's
ICS '94 Proceedings of the 8th international conference on Supercomputing
Resource allocation in a high clock rate microprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
The 16-fold way: a microparallel taxonomy
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Dynamically scheduled VLIW processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
An evaluation of functional unit lengths for single-chip processors
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A VLIW architecture based on shifting register files
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Vector architectures: past, present and future
ICS '98 Proceedings of the 12th international conference on Supercomputing
Decoupled access/execute computer architectures
25 years of the international symposia on Computer architecture (selected papers)
Implementation of precise interrupts in pipelined processors
25 years of the international symposia on Computer architecture (selected papers)
The University of Manchester MU5 Project
IEEE Annals of the History of Computing
MPS: Miss-Path Scheduling for Multiple-Issue Processors
IEEE Transactions on Computers
On the scheduling of variable latency functional units
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Implementation of precise interrupts in pipelined processors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Tagged architecture: how compelling are its advantages?
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Fault Tolerant Operating Systems
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
Ethernet: distributed packet switching for local computer networks
Communications of the ACM - Special 25th Anniversary Issue
Memory management and response time
Communications of the ACM
Relational profiling: enabling thread-level parallelism in virtual machines
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Ethernet: distributed packet switching for local computer networks
Communications of the ACM
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications
IEEE Transactions on Computers
The pyramid teaching computer structures by computer structures
ACM SIGCSE Bulletin
IEEE Micro
IEEE Micro
Interrupt Handling for Out-of-Order Execution Processors
IEEE Transactions on Computers
Process exchange on the PR1ME family of computers
ACM SIGARCH Computer Architecture News
The microprocessors of the future
ACM SIGARCH Computer Architecture News
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
An EPIC Processor with Pending Functional Units
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Analysis of Cray-1S architecture
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Decoupled access/execute computer architectures
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A language implementation design for a multiprocessor computer system
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A large-scale dual operating system
ACM '73 Proceedings of the ACM annual conference
An experimental study of computer system performance
ACM '72 Proceedings of the ACM annual conference - Volume 2
Graph models of computer systems: Application to performance evaluation of an operating system
SIGMETRICS '76 Proceedings of the 1976 ACM SIGMETRICS conference on Computer performance modeling measurement and evaluation
A language-oriented instruction set for the BALM language
Proceedings of the meeting on SIGPLAN/SIGMICRO interface
Describing program behavior in a multiprogramming computer system
ANSS '75 Proceedings of the 3rd symposium on Simulation of computer systems
Experience with trace driven modeling
ANSS '76 Proceedings of the 4th symposium on Simulation of computer systems
Run-time characteristics of a simulation model
ANSS '76 Proceedings of the 4th symposium on Simulation of computer systems
Instruction issue logic for pipelined supercomputers
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An adaptive subdivision algorithm and parallel architecture for realistic image synthesis
SIGGRAPH '84 Proceedings of the 11th annual conference on Computer graphics and interactive techniques
A linear-time algorithm for a special case of disjoint set union
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Analysis of a time-sharing subsystem (A Preliminary Report)
SIGMETRICS '74 Proceedings of the 1974 ACM SIGMETRICS conference on Measurement and evaluation
Multiprocessor hardware: An architectural overview
ACM '80 Proceedings of the ACM 1980 annual conference
Predicting concurrent computer system performance using Petri-Net models
ACM '78 Proceedings of the 1978 annual conference - Volume 2
The modular logic machine design system for loosely coupled systems
ACM '77 Proceedings of the 1977 annual conference
Gathering and analyzing data from a computer system: A case study
ACM '75 Proceedings of the 1975 annual conference
A multi-microprocessor implementation of a general purpose pipelined CPU
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Simulation of computer systems using automatically generated load descriptions
WSC '74 Proceedings of the 7th conference on Winter simulation - Volume 2
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Scalable Hardware Memory Disambiguation for High ILP Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
SICOSIM3 Proceedings of the third annual symposium on SIGCOSIM: Major issues confronting managers of computer resources
Programmable bus/memory controllers in modern computer architecture
Proceedings of the 43rd annual Southeast regional conference - Volume 1
U-Net/SLE: A Java-based user-customizable virtual network interface
Scientific Programming
A Restructurable Computer System
IEEE Transactions on Computers
Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder
IEEE Transactions on Computers
Overlapped Operation with Microprogramming
IEEE Transactions on Computers
The Burroughs Scientific Processor (BSP)
IEEE Transactions on Computers
Highlights of a Study of Floating-Point Instructions
IEEE Transactions on Computers
Instruction Issue Logic in Pipelined Supercomputers
IEEE Transactions on Computers
Maurer computers for pipelined instruction processing†
Mathematical Structures in Computer Science
A study of response times under various deadlock algorithms and job schedulers
ACM '74 Proceedings of the 1974 annual ACM conference - Volume 2
Validation of a trace-driven CDC 6400 simulation
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
The interaction of multi-programming job scheduling and CPU scheduling
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
The Control Data® STAR-100 file storage station
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
The architecture of MANIP: a parallel computer system for solving NP-complete problems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Robustly secure computer systems: a new security paradigm of system discontinuity
NSPW '07 Proceedings of the 2007 Workshop on New Security Paradigms
Helios: heterogeneous multiprocessing with satellite kernels
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
The Modeling and Design of Multiple Function-Unit Processors
IEEE Transactions on Computers
MIPS MT: a multithreaded RISC architecture for embedded real-time processing
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
On the operating unit size of load/store architectures†
Mathematical Structures in Computer Science
An Instruction Fetch Unit for a High-Performance Personal Computer
IEEE Transactions on Computers
Static speculation as post-link optimization for the Grid Alu processor
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
A shared matrix unit for a chip multi-core processor
Journal of Parallel and Distributed Computing
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