Communications of the ACM - Special issue on computer architecture
Performance evaluation of highly concurrent computers by deterministic simulation
Communications of the ACM
Application of GPSS Five to Discrete System Simulation
Application of GPSS Five to Discrete System Simulation
A simulation environment for performing dataflow research
SIGMETRICS '79 Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems
Analysis and design of pipelined processors.
Analysis and design of pipelined processors.
An extended abstract dataflow methodology for designing and modeling reconfigurable systems
An extended abstract dataflow methodology for designing and modeling reconfigurable systems
Design of a Computer—The Control Data 6600
Design of a Computer—The Control Data 6600
A Formal Definition of Data Flow Graph Models
IEEE Transactions on Computers
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
A two-tier memory architecture for high-performance multiprocessor systems
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
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An analysis of the Cray-1S architecture based on dataflow graphs is presented. The approach consists of representing the components of a Cray-1S system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the dataflow graph. The elapsed time and the resources used in a component are represented by the attributes of the node corresponding to the component. The resulting dataflow graph model is simulated to obtain timing statistics using as input a control stream that represents the instruction and data stream of the real computer system. The Cray-1S architecture is analyzed by conducting several experiments with the model. It is observed that the architecture is a well balanced one and performance improvements are hard to achieve without major changes. Significant improvement in performance is shown when parallel instruction issue is allowed with multiple CIP/LIPs in the architecture.