Parallel processing: the Cm* experience
Parallel processing: the Cm* experience
Designing efficient algorithms for parallel computers
Designing efficient algorithms for parallel computers
Proceedings of the international workshop on Parallel algorithms & architectures
Matrix operations on a multicomputer system with switchable main memory modules and dynamic control
IEEE Transactions on Computers
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
A bit-plane architecture for optical computing with two-dimensional symbolic substitution
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Exploiting parallel microprocessor microarchitectures with a compiler code generator
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The VMP multiprocessor: initial experience, refinements, and performance evaluation
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The connection machines CM-1 and CM-2: solving nonlinear network problems
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Static synchronization beyond VLIW
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
A case study in programming for parallel-processors
Communications of the ACM
Performance of various computers using standard linear equations software
ACM SIGARCH Computer Architecture News
Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System
IEEE Transactions on Parallel and Distributed Systems
Analysis of Cray-1S architecture
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
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Experimentation aimed at determining the potential benefit of mixed-mode SIMD/MIMD parallel architectures is reported. The experimentation is based on timing measurements made on the PASM system prototype at Purdue utilizing carefully coded synthetic variations of a well-known algorithm. The synthetic algorithms used to measure and evaluate this system were based on bitonic sorting of sequences stored in the processing elements. This computation was mapped to both the SIMD and MIMD modes of parallelism, as well as two hybrids of the SIMD and MIMD modes. The computations were coded in these four ways and experiments were performed that explore the trade-offs among them. The results of these experiments are presented and are discussed with special consideration of the effects of the system's architecture. The goal is to (as much as possible) obtain implementation independent analyses of the attributes of mixed-mode parallel processing with respect to the computational characteristics of the application being examined. The results are used to gain insight into the impact of computation mode on synchronization and data-conditional aspects of system performance.