Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
Computer
Multiprocessor cache synchronization: issues, innovations, evolution
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Concurrent Prolog: A Progress Report
Computer
Applications considerations in the system design of highly concurrent multiprocessors
IEEE Transactions on Computers
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Communications of the ACM - Special issue on computer architecture
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Analysis of Cray-1S architecture
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A Characterization of Sharing In Parallel Programs And Its
A Characterization of Sharing In Parallel Programs And Its
The and/or process model for parallel interpretation of logic programs
The and/or process model for parallel interpretation of logic programs
High performance execution of prolog programs based on a static data dependency analysis (and-parallelism, semi-intelligent backtracking)
A parallel execution model for prolog
A parallel execution model for prolog
Aspects of cache memory and instruction buffer performance
Aspects of cache memory and instruction buffer performance
Computer system organization: The B5700/B6700 series (ACM monograph series)
Computer system organization: The B5700/B6700 series (ACM monograph series)
Multiple vs. wide shared bus multiprocessors
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
C2MP: a cache-coherent, distributed memory multiprocessor-system
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
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Performance of high-speed multiprocessor systems is limited by the available bandwidth to memory and the need to synchronize write sharable data. This paper presents a new memory system that separates synchronization related data from others. The memory system has two tiers: synchronization memory and high bandwidth (HB) memory. The synchronization memory consists of snooping caches connected to a bus and is used to store synchronization variables such as locks and semaphores. The HB memory is used to store the bulk of the application program code and data. It contains caches and a high bandwidth interconnection network to memory, such as the crossbar, but does not have full snooping among caches.The two tier memory system has been evaluated by analyzing the memory behavior of the simulated parallel execution of Prolog programs. Initial results indicate that the two tier memory system potentially reduces memory interference and speeds up synchronization. Three different schemes have been studied for the caches on the HB memory and the results are presented. The two-tier memory system has potential applications in areas where synchronization is light to medium and local data is often accessed.