Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Contention is no obstacle to shared-memory multiprocessing
Communications of the ACM - Special issue on parallelism
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The cache coherence problem in shared-memory multiprocessors
The cache coherence problem in shared-memory multiprocessors
A Generalized Timed Petri Net Model for Performance Analysis
IEEE Transactions on Software Engineering
Firefly: A Multiprocessor Workstation
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Multiprocessor cache analysis using ATUM
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A cache coherence scheme with fast selective invalidation
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A Case for Direct-Mapped Caches
Computer
An overview of the Kyushu University reconfigurable parallel processor
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A two-tier memory architecture for high-performance multiprocessor systems
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Memory-reference characteristics of multiprocessor applications under MACH
SIGMETRICS '88 Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Analysis of cache invalidation patterns in multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Specification and properties of a cache coherence protocol model
Advances in Petri Nets 1987, covers the 7th European Workshop on Applications and Theory of Petri Nets
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons
ACM Computing Surveys (CSUR)
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Current research into the problems of cache coherency in multiprocessor (MP) systems, has primarily focused on bus based memory interconnection networks (M-ICN) and the use of various types of “snooping” cache coherency protocols. Bus bandwidth limitations can be alleviated through the use of wider bandwidth general interconnection structures, such as a crossbar switch. However, if private caches are used, the cache coherency problem becomes multiply compounded. Little work has been done to address this problem.A new distributed shared-memory multiprocessor system with private caches and for use with general memory interconnection networks (M-ICNs) is presented. A new distributed cache coherency-controller ($-K) unit is employed to manage coherency invalidation/updating over a dedicated bus based coherency interconnection network (C-ICN). This allows for cache-to-cache coherency updating to reduce the M-ICN traffic to only that of instruction/data transactions. This architecture incorporates a unique hierarchical, preemptive cache coherency protocol, simple enough to be implemented in hardware. A feasible implementation of a fully asynchronous crossbar switch is also presented as a possible general memory interconnection network (M-ICN).