An overview of the Kyushu University reconfigurable parallel processor

Authors:
Kazuaki Murakami;Akira Fukuda;Toshinori Sueyoshi;Shinji Tomita
Affiliations:
Department of Information Systems, Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Kasuga, Fukuoka, 816 JAPAN;Department of Information Systems, Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Kasuga, Fukuoka, 816 JAPAN;Department of Information Systems, Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Kasuga, Fukuoka, 816 JAPAN;Department of Information Systems, Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Kasuga, Fukuoka, 816 JAPAN
Venue:
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
Year:
1988

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Abstract

As a testbed to investigate systemwide aspects of highly parallel processing, a reconfigurable parallel processor system is currently developed at the Kyushu University in Japan. The system is a MIMD- type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N×N crossbar networks (currently S is 1). Each processing-element (PE) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set and 4 Mbytes of memory. Although memory are organized to be distributed among all PEs, the system can be reconfigured as either a memory-shared tightly coupled multiprocessor or a message-passing loosely coupled multiprocessor at run time; also as a hybrid of the two. The crossbar network allows users to take arbitrary topologies for inter-PE (i.e. processor-memory and/or processor-processor) paths under software control of an operating system. The parallel/distributed operating system is also under development to exploit parallelism by making the best of reconfigurability. The full 128-PE configuration will provide up to 1.28 GIPS, 205 MFLOPS (single precision LINPACK), 141 MFLOPS (double precision LINPACK), 512 Mbytes of memory and 1.28 Gbytes/s inter-PE communication. This paper outlines the reconfigurable network and memory architectures among several unique architectural features of the reconfigurable parallel processor.