Optical interconnection using ShuffleNet multihop networks in multi-connected ring topologies
SIGCOMM '88 Symposium proceedings on Communications architectures and protocols
An analysis of Memnet—an experiment in high-speed shared-memory local networking
SIGCOMM '88 Symposium proceedings on Communications architectures and protocols
A survey of commercial parallel processors
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
The Flex architecture, a high speed graphics processor
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
An overview of the Kyushu University reconfigurable parallel processor
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
Queuing analysis of polling models
ACM Computing Surveys (CSUR)
Computer Networks and ISDN Systems
Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
Multicomputer interconnection using word parallel shift register ring networks
Multicomputer interconnection using word parallel shift register ring networks
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This paper discusses the design of a switch for high-speed computer networking at gigabit rates. We present the Pulsar switch, a non-blocking design based on a high-spin-rate, port-dedicated, word-parallel, shift-register ring. Several design alternatives address the problem of Head-Of-Line blocking. In contrast to Batcher-Banyan switches, access to the ring is asynchronous which facilitates low delay and arbitrary packet length. The switch can support ATM cells simultaneously with packets sized for applications such as single characters, memory words, disk blocks, memory pages, or video images. Pulsar can be used as a high-throughput computer backplane replacement. The design can be implemented with existing high-speed circuit technology.