Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Empirical analysis of the mesa instruction set
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Register windows vs. register allocation
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
ParcBench: a benchmark for shared-memory architectures
ACM SIGARCH Computer Architecture News
Experiences creating a portable cedar
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Organization and performance of a two-level virtual-real cache hierarchy
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
C2MP: a cache-coherent, distributed memory multiprocessor-system
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design choices for the TOP-1 multiprocessor workstation
IBM Journal of Research and Development
Register windows vs. register allocation
ACM SIGPLAN Notices - Best of PLDI 1979-1999
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The Xerox PARC Dragon is a VLSI research computer that uses several techniques to achieve dense code and fast procedure calls in a system that can support multiple processors on a central high bandwidth memory bus.