RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Code selection through object code optimization
ACM Transactions on Programming Languages and Systems (TOPLAS) - Lecture notes in computer science Vol. 174
A retargetable instruction reorganizer
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
An instruction fetch unit for a graph reduction machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
On the use of registers vs. cache to minimize memory traffic
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Highly concurrent scalar processing
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Branch folding in the CRISP microprocessor: reducing branch delay to zero
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of branch architectures
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
WISQ: a restartable architecture using queues
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The hardware architecture of the CRISP microprocessor
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Case study: IBM's system/360-370 architecture
Communications of the ACM
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Integer multiplication and division on the HP precision architecture
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The Mahler experience: using an intermediate language as the machine description
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
ACM SIGARCH Computer Architecture News
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Integer Multiplication and Division on the HP Precision Architecture
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Analysis of memory referencing behavior for design of local memories
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
An introduction to function rank
APL '88 Proceedings of the international conference on APL
Computer
Flexible processors: a promising application-specific processor design approach
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Improving performance of small on-chip instruction caches
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Machine organization of the IBM RISC System/6000 processor
IBM Journal of Research and Development
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
The interaction of architecture and operating system design
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Code generation for streaming: an access/execute mechanism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Cache write policies and performance
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
History of the PowerPC architecture
Communications of the ACM
The PowerPC 603 microprocessor
Communications of the ACM
Evolution of the PowerPC Architecture
IEEE Micro
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Control flow optimization for supercomputer scalar processing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
LISP on a reduced-instruction-set-processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Optimal code generation for expressions on super scalar machines
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
SH3: High Code Density, Low Power
IEEE Micro
Efficient Instruction Sequencing with Inline Target Insertion
IEEE Transactions on Computers
An analysis of C machine support for other block-structured languages
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Keynote address - the processor instruction set
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
MIPS: A microprocessor architecture
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A retrospective on the Dorado, a high-performance personal computer
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Adaptive interpretation as a means of exploiting complex instruction sets
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
RISC assessment: A high-level language experiment
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Hints for computer system design
SOSP '83 Proceedings of the ninth ACM symposium on Operating systems principles
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Peering through the RISC/CISC fog: an outline of research
ACM SIGARCH Computer Architecture News
An overview of the PL.8 compiler
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Optimization of range checking
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Register allocation and spilling via graph coloring
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Global register allocation at link time
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Register windows vs. register allocation
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Reduced instruction set computer (RISC)
Encyclopedia of Computer Science
HLLDA defies RISC: thoughts on RISCs, CISCs, and HLLDAs
ACM SIGMICRO Newsletter
The NYU Ultracomputer Designing an MIMD Shared Memory Parallel Computer
IEEE Transactions on Computers
Integration of machine organization and control program design: review and direction
IBM Journal of Research and Development
Data hiding in compiled program binaries for enhancing computer system performance
IH'05 Proceedings of the 7th international conference on Information Hiding
ASC: automatically scalable computation
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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This paper provides an overview of an experimental system developed at the IBM T. J. Watson Research Center. It consists of a running hardware prototype, a control program and an optimizing compiler. The basic concepts underlying the system are discussed as are the performance characteristics of the prototype. In particular, three principles are examined: system orientation towards the pervasive use of high level language programming and a sophisticated compiler, a primitive instruction set which can be completely hard-wired, storage hierarchy and I/O organization to enable the CPU to execute an instruction at almost every cycle.