IBM RISC System/6000: Architecture and Performance

  • Authors:
  • Richard R. Oehler;Michael W. Blasgen

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Micro
  • Year:
  • 1991

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Abstract

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.