Computer
A high speed superscalar PA-RISC processor
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Pathlength reduction features in the PA-RISC architecture
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
IEEE Micro
CMOS Processor Circuit Design in Hewlett-Packard's Series 700 Workstations
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
MOB forms: a class of multilevel block algorithms for dense linear algebra operations
ICS '94 Proceedings of the 8th international conference on Supercomputing
Complexity/performance tradeoffs with non-blocking loads
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The effects of predicated execution on branch prediction
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Analysis of the conditional skip instructions of the HP precision architecture
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
DAC '94 Proceedings of the 31st annual Design Automation Conference
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
ACM SIGARCH Computer Architecture News
Cache performance of fast-allocating programs
FPCA '95 Proceedings of the seventh international conference on Functional programming languages and computer architecture
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
An analytical model of high performance superscalar-based multiprocessors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Increasing cache port efficiency for dynamic superscalar microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Optimization of machine descriptions for efficient use
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Eliminating cache conflict misses through XOR-based placement functions
ICS '97 Proceedings of the 11th international conference on Supercomputing
Performance analysis of tree VLIW architecture for exploiting branch ILP in non-numerical code
ICS '97 Proceedings of the 11th international conference on Supercomputing
Designing high bandwidth on-chip caches
Proceedings of the 24th annual international symposium on Computer architecture
Division Algorithms and Implementations
IEEE Transactions on Computers
Proceedings of the 25th annual international symposium on Computer architecture
Optimization of Machine Descriptions for Efficient Use
International Journal of Parallel Programming
IEEE Micro
U-cache: a cost-effective solution to synonym problem
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
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The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed.