Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
BYTE
ACM Computing Surveys (CSUR)
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
The MIPS R3010 Floating-Point Coprocessor
IEEE Micro
MIPS: a VLSI processor architecture
MIPS: a VLSI processor architecture
A simulation based study of TLB performance
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The effect of page allocation on caches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Complexity/performance tradeoffs with non-blocking loads
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Quantitative Evaluation of Register Pressure on Software Pipelined Loops
International Journal of Parallel Programming
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Non-Consistent Dual Register Files to Reduce Register Pressure
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Program balance and its impact on high performance RISC architectures
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Locking with Different Granularities for Reads and Writes in an MVM System
IDEAS '99 Proceedings of the 1999 International Symposium on Database Engineering & Applications
Multi-view memory to support OS locking for transaction systems
IDEAS'97 Proceedings of the 1997 international conference on International database engineering and applications symposium
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The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip