Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Communications of the ACM
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The effect of employing advanced branching mechanisms in superscalar processors
ACM SIGARCH Computer Architecture News
The MC88110 implementation of precise exceptions in a superscalar architecture
ACM SIGARCH Computer Architecture News
Empirical evaluation of some features of instruction set processor architectures
Communications of the ACM
IEEE Micro
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
On the Performance Evaluation of Fully Asynchronous Processor Architectures
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Static Scheduling of Instructions on Micronet-based Asynchronous Processors
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
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Micronets model processor architectures as a network of communicating resources, in contrast to the traditional one of a linear pipeline. Micronets distribute the control to the functional units, which enables the exploitation of fine-grain concurrency between instructions. The overhead due to asynchrony is hidden with the four-phase protocol being used to implement scoreboarding and hazard avoidance mechanisms, without incurring additional control costs. This paper demonstrates the feasibility of micronet-based processors. Results are presented for SPICE-level simulations of a 0.7 /spl mu/m CMOS implementation of a datapath. The relationships between micronets and both the compiler and the computer architecture are also explored.