ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Limits on multiple instruction issue
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
RISC architecture: a perspective on the past and future
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Boosting beyond static scheduling in a superscalar processor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
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This paper discusses the effect of employing advanced branching mechanisms in superscalar processors. The motivation behind employing advanced branching mechanisms in superscalar processors is to reduce the control dependence, or in other words the number of branch operations, in the program so that instruction-level parallelism can be exploited more effectively. The second effect achieved by reducing the control dependence in the program is a decrease of the amount of branch penalty due to less branch operations. In this paper, two advanced branching mechanisms are discussed. The first mechanism involves incorporating multiple condition registers in superscalar processors. The second mechanism is a novel multi-way branching scheme proposed in this paper. A quantitative analysis on the effect of the two branching mechanisms shows that incorporating multiple condition registers can boost the superscalar processor performance by a factor of 16% to 20% while employing the proposed multi-way branching mechanism can achieve even greater performance improvement, up to 47%.