Empirical evaluation of some features of instruction set processor architectures
Communications of the ACM
ACM SIGARCH Computer Architecture News
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
IEEE Transactions on Computers
Computer instruction set usage by programmers: an empirical investigation
Communications of the ACM
Microprocessor architectures: a comparison based on code generation by compiler
Communications of the ACM
Register allocation in the SPUR Lisp compiler
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Microprogrammable processor for object-oriented architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An instruction fetch unit for a graph reduction machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Fast object-oriented procedure calls: lessons from the Intel 432
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An in-cache address translation mechanism
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
On the use of registers vs. cache to minimize memory traffic
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Multiprocessor cache synchronization: issues, innovations, evolution
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
The microarchitecture of a capability-based computer
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
A perspective on the 801/Reduced Instruction Set Computer
IBM Systems Journal
Coming to grips with a RISC: a report of the progress of the LOW RISC design group
ACM SIGARCH Computer Architecture News
Use of instruction set simulators to evaluate the LOW RISC
ACM SIGARCH Computer Architecture News
SOAR: Smalltalk without bytecodes
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Cint: a RISC interpreter for the C programming language
SIGPLAN '87 Papers of the Symposium on Interpreters and interpretive techniques
Cache design of a sub-micron CMOS system/370
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Performance evaluation of multiple register sets
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
An architecture for the direct execution of the Forth programming language
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Integer multiplication and division on the HP precision architecture
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The Mahler experience: using an intermediate language as the machine description
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A vector hardware accelerator with circuit simulation emphasis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
Measurement and evaluation of the MIPS architecture and processor
ACM Transactions on Computer Systems (TOCS)
Parallel Discrete Event Simulation Using Shared Memory
IEEE Transactions on Software Engineering
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Integer Multiplication and Division on the HP Precision Architecture
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Register windows vs. register allocation
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Minimizing register usage penalty at procedure calls
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Computer
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
An efficient pipelined dataflow processor architecture
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Improving Quicksort Performance with a Codeword Data Structure
IEEE Transactions on Software Engineering
The fuzzy barrier: a mechanism for high speed synchronization of processors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Using registers to optimize cross-domain call performance
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The effect of sharing on the cache and bus performance of parallel programs
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Micro-optimization of floating-point operations
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Optimal code generation for expression trees: an application BURS theory
POPL '88 Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Unified management of registers and cache using liveness and cache bypass
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Evaluating the performance of four snooping cache coherency protocols
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Supporting reference and dirty bits in SPUR's virtual address cache
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
On the Minimization of Loads/Stores in Local Register Allocation
IEEE Transactions on Software Engineering
Scheduling time-critical instructions on RISC machines
POPL '90 Proceedings of the 17th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An Overview of Common Benchmarks
Computer
Concurrency + modularity + programmability = MARS
Communications of the ACM - Special issue: Soviet computing
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Branch history table prediction of moving target branches due to subroutine returns
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
The effect of employing advanced branching mechanisms in superscalar processors
ACM SIGARCH Computer Architecture News
GRIP: graphics reduced instruction processor
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Simplicity Versus Accuracy in a Model of Cache Coherency Overhead
IEEE Transactions on Computers
Distributed Instruction Set Computer Architecture
IEEE Transactions on Computers
An integrated memory management scheme for dynamic alias resolution
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
A semantics-directed partitioning of a processor architecture
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
An overview of RISC architecture
SAC '92 Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990's
Performance evaluation of instruction scheduling on the IBM RISC System/6000
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
StaCS: a Static Control Superscalar architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register relocation: flexible contexts for multithreading
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
Design at the system level with VLSI CMOS
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Performance effects of architectural complexity in the Intel 432
ACM Transactions on Computer Systems (TOCS)
Efficient and language-independent mobile programs
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Strategic directions in computer architecture
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
An evaluation of functional unit lengths for single-chip processors
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Microprogramming heritage of RISC design
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Parallelizing nonnumerical code with selective scheduling and software pipelining
ACM Transactions on Programming Languages and Systems (TOPLAS)
A fault tolerant, bit-parallel, cellular array processor
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Optimal code generation for expressions on super scalar machines
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Retargetable high-level alias analysis
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
High-performance extendable instruction set computing
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Verifying a Multiprocessor Cache Controller Using Random Test Generation
IEEE Design & Test
IEEE Micro
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
IEEE Transactions on Computers
Concurrent Process Monitoring with No Reference Signatures
IEEE Transactions on Computers
Do Object-Oriented Languages Need Special Hardware Support?
ECOOP '95 Proceedings of the 9th European Conference on Object-Oriented Programming
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Cross-Architectural Performance Portability of a Java Virtual Machine Implementation
Proceedings of the 2nd Java Virtual Machine Research and Technology Symposium
A methodology to design programmble embedded systems: the Y-chart approach
Embedded processor design challenges
Global register allocation at link time
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Register windows vs. register allocation
ACM SIGPLAN Notices - Best of PLDI 1979-1999
A Tale of Two Processors: Revisiting the RISC-CISC Debate
Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Using a configurable processor generator for computer architecture prototyping
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Towards Time-Predictable Data Caches for Chip-Multiprocessors
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Paper: A detailed look at some popular benchmarks
Parallel Computing
Evaluating the performance of space plasma simulations using FPGA's
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
WCET driven design space exploration of an object cache
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Typed assembler for a RISC crypto-processor
ESSoS'12 Proceedings of the 4th international conference on Engineering Secure Software and Systems
On the scalability of time-predictable chip-multiprocessing
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Data cache organization for accurate timing analysis
Real-Time Systems
A fully homomorphic crypto-processor design: correctness of a secret computer
ESSoS'13 Proceedings of the 5th international conference on Engineering Secure Software and Systems
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Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.