Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
The VAL Language: Description and Analysis
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
DATA FLOW COMPUTER ARCHITECTURE FINAL REPORT
DATA FLOW COMPUTER ARCHITECTURE FINAL REPORT
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration
IEEE Transactions on Computers
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A design study of the EARTH multiprocessor
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Towards efficient fine-grain software pipelining
ICS '90 Proceedings of the 4th international conference on Supercomputing
Analysis of integration models for service composition
WOSP '02 Proceedings of the 3rd international workshop on Software and performance
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Evaluating use of data flow systems for large graph analysis
Proceedings of the 2nd Workshop on Many-Task Computing on Grids and Supercomputers
WSEAS Transactions on Computers
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A stream-computing extension to OpenMP
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
For extreme parallelism, your OS is Sooooo last-millennium
HotPar'12 Proceedings of the 4th USENIX conference on Hot Topics in Parallelism
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This paper demonstrates that the principles of pipelined instruction execution can be effectively applied in dataflow computers, yielding an architecture that avoids the main sources of pipeline gaps during program execution in many conventional processor designs. The new processing element design uses an architecture called argument-fetch dataflow architecture. It has two parts: a dataflow instruction scheduling unit (DISU) and a pipelined instruction processing unit (PIPU). The PIPU is an instruction processor that uses many conventional techniques to achieve fast pipelined operation. The DISU holds the dataflow signal graph of the collection of dataflow instructions allocated to the processing element, and maintains a large pool of enabled instructions available for execution by the PIPU. The new architecture provides a basis for achieving high performance for many scientific applications. To show that the realization of an efficient dataflow processing element is feasible, a trial design and fabrication of an enable memory-a key component of the DISU-is reported.