Annual review of computer science vol. 1, 1986
ACM Computing Surveys (CSUR)
An efficient pipelined dataflow processor architecture
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
The Epsilon dataflow processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The RMIT data flow computer: a hybrid architecture
The Computer Journal - Special issue on parallel computing
Multithreading: a revisionist view of dataflow architectures
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Retrospective: a preliminary architecture for a basic data flow processor
25 years of the international symposia on Computer architecture (selected papers)
The specification of a new Manchester Dataflow machine
ICS '89 Proceedings of the 3rd international conference on Supercomputing
A design space evaluation of grid processor architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A History of Data-Flow Languages
IEEE Annals of the History of Computing
A Comparative Study of Data-Flow Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Area-Performance Trade-offs in Tiled Dataflow Architectures
Proceedings of the 33rd annual international symposium on Computer Architecture
ACM Transactions on Computer Systems (TOCS)
Computer
Practical fpga programming in c
Practical fpga programming in c
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
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Different from traditional processors, Moorés Law was one of the reasons to duplicate cores, and at least until today it is the solution for safe consumption and operation of systems using millions of transistors. In terms of software, parallelism will be a tendency over the coming years. One of the challenges is to create tools for programmers who use HLL (High Level Language) producing hardware directly. These tools should use the utmost experience of the programmers and the flexibility of FPGA (Field Programmable Gate Array). The main aspect of the existing tools which directly convert HLL into hardware is dependence graphics. On the other hand, a dynamic dataflow architecture has implicit parallelism. ChipCflow is a tool to convert C directly into hardware that uses FPGA as a partial reconfiguration based on a dynamic dataflow architecture. In this paper, the relation between traditional dataflow architecture and contemporary architecture, as well as the main characteristics of the ChipCflow project will be presented.