The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
A GRAPH MODEL FOR PARALLEL COMPUTATIONS
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PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
TWIST-TOP: transputers with I-stores test out processor
CSC '90 Proceedings of the 1990 ACM annual conference on Cooperation
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
T: integrated building blocks for parallel computing
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Ideograph/Ideogram: framework/hardware for eager evaluation
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Iterative Instructions in the Manchester Dataflow Computer
IEEE Transactions on Parallel and Distributed Systems
A Hybrid Scheme for Processing Data Structures in a Dataflow Environment
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Hardware-modulated parallelism in chip multiprocessors
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Proceedings of the 33rd annual international symposium on Computer Architecture
Area-Performance Trade-offs in Tiled Dataflow Architectures
Proceedings of the 33rd annual international symposium on Computer Architecture
Modeling instruction placement on a spatial architecture
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
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Proceedings of the 15th international conference on Parallel architectures and compilation techniques
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ACM Transactions on Computer Systems (TOCS)
WSEAS Transactions on Computers
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The &egr;psilon dataflow architecture is designed for high speed uniprocessor execution as well as for parallel operation in a multiprocessor system. The &egr;psilon architecture directly matches ready operands, thus eliminating the need for associative matching stores. &egr;psilon also supports low cost data fan out and critical sections. A 10 MFLOPS CMOS/TTL processor prototype is running and its performance has been measured with several benchmarks. The prototype processor has demonstrated sustained performance exceeding that of comparable control flow processors running at higher clock rates (three times faster than a 20 Mhz transputer and 24 times faster than a Sun on a suite of arithmetic tests, for example).