TWIST-TOP: transputers with I-stores test out processor

Authors:
George S. Davidson
Affiliations:
Sandia National Laboratories, Albuquerque, New Mexico
Venue:
CSC '90 Proceedings of the 1990 ACM annual conference on Cooperation
Year:
1990

Citing 5
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Abstract

Future parallel computing systems will require high speed communication, efficient synchronization primitives, and low overhead context switches for communicating and synchronizing instruction streams. These issues are developed with respect to I-storage, a global memory that can synchronize requests for data values issued before the data is produced. Methods to implement these I-stores are described for the transputer architecture, with programs and timing results. This description, for both single and multiprocessors, includes a discussion of run-time systems requiring no extra hardware. However, simple hardware extensions are also proposed, which will provide faster implementations. This hardware is expected to be much less expensive than a custom dataflow machine, allowing a larger research community to experiment with dataflow languages and applications.