The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Lambda lifting: transforming programs to recursive equations
Proc. of a conference on Functional programming languages and computer architecture
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
MASA: a multithreaded processor architecture for parallel symbolic computing
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Two fundamental issues in multiprocessing
4th International DFVLR Seminar on Foundations of Engineering Sciences on Parallel Computing in Science and Engineering
Executing a Program on the MIT Tagged-Token Dataflow Architecture
IEEE Transactions on Computers
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Communications of the ACM - Special issue on computer architecture
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A COMPILER FOR THE MIT TAGGED-TOKEN DATAFLOW ARCHITECTURE
A COMPILER FOR THE MIT TAGGED-TOKEN DATAFLOW ARCHITECTURE
Analysis of multithreaded architectures for parallel computing
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Functional Data Structures as Updatable Objects
IEEE Transactions on Software Engineering
TWIST-TOP: transputers with I-stores test out processor
CSC '90 Proceedings of the 1990 ACM annual conference on Cooperation
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Multithreading: a revisionist view of dataflow architectures
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Executing DSP Applications in a Fine-Grained Dataflow Environment
IEEE Transactions on Software Engineering
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
The expandable split window paradigm for exploiting fine-grain parallelsim
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
An elementary processor architecture with simultaneous instruction issuing from multiple threads
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Thread-based programming for the EM-4 hybrid dataflow machine
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Improved multithreading techniques for hiding communication latency in multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Evaluation of the WM architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
On the limits of program parallelism and its smoothability
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Microarchitecture support for dynamic scheduling of acyclic task graphs
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Register relocation: flexible contexts for multithreading
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Data stream control optimization in dataflow architectures
ICS '93 Proceedings of the 7th international conference on Supercomputing
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A design study of the EARTH multiprocessor
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Multithreading with Distributed Functional Units
IEEE Transactions on Computers
A basic architecture supporting LGDG computation
ICS '90 Proceedings of the 4th international conference on Supercomputing
Monsoon: an explicit token-store architecture
25 years of the international symposia on Computer architecture (selected papers)
Simultaneous multithreading: maximizing on-chip parallelism
25 years of the international symposia on Computer architecture (selected papers)
Monsoon: an explicit token-store architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Fine-Grained Multithreading with Process Calculi
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Efficient parallel global garbage collection on massively parallel computers
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Cache Memories for Dataflow Systems
IEEE Parallel & Distributed Technology: Systems & Technology
A Hybrid Scheme for Processing Data Structures in a Dataflow Environment
IEEE Transactions on Parallel and Distributed Systems
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
QR factorization for shared memory and message passing
Parallel Computing
The Named-State Register File: Implementation and Performance
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Fine-grain multi-thread processor architecture for massively parallel processing
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Performance Study of a Multithreaded Superscalar Microprocessor
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Mini-Threads: Increasing TLP on Small-Scale SMT Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Advances in dataflow programming languages
ACM Computing Surveys (CSUR)
Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
A low cost, multithreaded processing-in-memory system
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Multithreaded architecture for multimedia processing
Integrated Computer-Aided Engineering
Multi-threading and one-sided communication in parallel LU factorization
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Cache management for discrete processor architectures
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
Software data-triggered threads
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management
Microprocessors & Microsystems
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We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?” Starting with a simple, “RISC-like” instruction set, we show how to change the underlying processor organization to make it multithreaded. Then, we extend it with three instructions that give it a fine-grained, dataflow capability. We call the result P-RISC, for “Parallel RISC.” Finally, we discuss memory support for such multiprocessors. We compare our approach to existing MIMD machines and to other dataflow machines.