Evaluation of the FACOM ALPHA Lisp machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
RISCs vs. CISCs for Prolog: a case study
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Improving performance of small on-chip instruction caches
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
R256: a research parallel processor for scientific computation
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Performance comparison of load/store and symmetric instruction set architectures
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Reducing the cost of branches by using registers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
An investigation of static versus dynamic scheduling
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Architecture of the Symbolics 3600
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Tagged architecture: how compelling are its advantages?
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Communications of the ACM - Special issue on computer architecture
MC 68020 32-Bit Microprocessor User's Manual
MC 68020 32-Bit Microprocessor User's Manual
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A vector and array multiprocessor extension of the sylvan architecture
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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The SPIRE-Architecture is designed for high speed uniprocessor execution of sequential problems as well for parallel multiprocessor systems where individual processors perform operations on complex data structures. The idea of SPIRE-Architecture lies in a new instruction format expanded by a dedicated execution clause and compilative instruction execution. To mirror this concept in practice some new components has been added to the hardware.The simulation results show that SPIRE can processes data up to 30 times faster than classic von Neumann processor and profits directly from complexity of used data structures. Programm code is about twice as compact as that of RISC processors. Furthermore, a proposed hardware concept and consistent rules of instruction coding allows compilers to generate very efficient code.