Processor architecture and cache performance
Processor architecture and cache performance
Evaluation of the SPUR Lisp architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Design tradeoffs to support the C programming language in the CRISP microprocessor
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Lisp on a reduced-instruction-set processor: characterization and optimization
Lisp on a reduced-instruction-set processor: characterization and optimization
Measurement and evaluation of the MIPS architecture and processor
ACM Transactions on Computer Systems (TOCS)
ACM Computing Surveys (CSUR)
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Analysis of cache performance for operating systems and multiprogramming
Analysis of cache performance for operating systems and multiprogramming
SPIRE: streaming processing with instructions release element
ACM SIGARCH Computer Architecture News
16-bit vs. 32-bit instructions for pipelined microprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Performance issues in correlated branch prediction schemes
Proceedings of the 28th annual international symposium on Microarchitecture
Automatic and efficient evaluation of memory hierarchies for embedded systems
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
SH3: High Code Density, Low Power
IEEE Micro
The Effect of Code Expanding Optimizations on Instruction Cache Design
IEEE Transactions on Computers
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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The widespread use of reduced-instruction-set computers has generated a lot of interest in the tradeoff between the density of an instruction set and the size of the instruction cache. In this paper we present and justify a method that predicts the cache performance for a wide range of architectures, based on the miss rate for a single architecture. When we apply the method to a number of cache organizations we find that changes in code density can have a dramatic impact on memory traffic, but that modest improvements in code density do not reduce program execution time significantly in a well-balanced system.