Organization and VLSI implementation of MIPS
Advances in VLSI and Computer Systems
Evaluation of the SPUR Lisp architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A portable compiler: theory and practice
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
ACM SIGARCH Computer Architecture News
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Measurement and analysis of instruction use in the VAX-11/780
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A case study of VAX-11 instruction set usage for compiler execution
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Comparative analysis of computer architectures
Comparative analysis of computer architectures
A portable machine-independent global optimizer--design and measurements
A portable machine-independent global optimizer--design and measurements
Code optimization of pipeline constraints
Code optimization of pipeline constraints
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
The design and development of a dynamic program behavior measurement tool for the Intel 8086/88
ACM SIGARCH Computer Architecture News
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
On the validity of trace-driven simulation for multiprocessors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
Pipelining and Bypassing in a VLIW Processor
IEEE Transactions on Parallel and Distributed Systems
Fred: An Architecture for a Self-Timed Decoupled Computer
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A stack addressing scheme based on windowing
ACM SIGARCH Computer Architecture News
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MIPS is a 32-bit processor architecture that has been implemented as an nMOS VLSI chip. The instruction set architecture is RISC-based. Close coupling with compilers and efficient use of the instruction set by compiled programs were goals of the architecture. The MIPS architecture requires that the software implement some constraints in the design that are normally considered part of the hardware implementation. This paper presents experimental results on the effectiveness of this processor as a program host. Using sets of large and small benchmarks, the instruction and operand usage patterns are examined both for optimized and unoptimized code. Several of the architectural and organizational innovations in MIPS, including software pipeline scheduling, multiple-operation instructions, and word-based addressing, are examined in light of this data.