Measurement and evaluation of the MIPS architecture and processor
ACM Transactions on Computer Systems (TOCS)
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Architecture and compiler tradeoffs for a long instruction wordprocessor
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Percolation Scheduling: A Parallel Compilation Technique
Percolation Scheduling: A Parallel Compilation Technique
Compaction-based parallelization
Compaction-based parallelization
The performance impact of incomplete bypassing in processor pipelines
Proceedings of the 28th annual international symposium on Microarchitecture
Exploiting data forwarding to reduce the power budget of VLIW embedded processors
Proceedings of the conference on Design, automation and test in Europe
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Performance evaluation for a compressed-VLIW processor
Proceedings of the 2002 ACM symposium on Applied computing
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Operation tables for scheduling in the presence of incomplete bypassing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Scalable register bypassing for FPGA-based processors
Microprocessors & Microsystems
Retargetable pipeline hazard detection for partially bypassed processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This short note describes issues involved in the bypassing mechanism for a very longinstruction word (VLIW) processor and its relation to the pipeline structure of theprocessor. The authors first describe the pipeline structure of their processor and analyzeits performance and compare it to typical RISC-style pipeline structures given the contextof a processor with multiple functional units. Next they study the performance effects ofvarious bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time.