Resource constrained dataflow retiming heuristics for VLIW ASIPs
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
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CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Parallel and Distributed Systems
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Instruction encoding synthesis for architecture exploration using hierarchical processor models
Proceedings of the 40th annual Design Automation Conference
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ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Customization of application specific heterogeneous multi-pipeline processors
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Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Processor Description Languages
Processor Description Languages
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Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instruction encoding schemes for multi-pipe Application Specific Instruction-Set Processors (ASIPs). Forwarding is a popular technique to reduce data hazards in the pipeline to improve performance and is applied in almost all modern processor designs; but it is very area expensive. Instruction encoding schemes have a direct impact on code size; an efficient encoding method can lead to a small instruction width, and hence reducing the code size. We propose application specific techniques to reduce forwarding networks and instruction widths for ASIPs with multiple pipelines. By these design techniques, it is possible to reduce area, code size, and even power consumption (due to reduced area), without costing any performance. Our experiments, on a set of benchmarks using the proposed customization approaches show that, on average, there are 27% savings on area, 30% on leakage power, 16.7% on code size, and at the same time, performance even improves by 4% because of the reduced clock period.