Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Feedback driven instruction-set extension
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
IEEE Transactions on Computers
Exploring the design space of LUT-based transparent accelerators
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Customization of application specific heterogeneous multi-pipeline processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Scalable subgraph mapping for acyclic computation accelerators
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Code transformation strategies for extensible embedded processors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Scientific applications vs. SPEC-FP: a comparison of program behavior
Proceedings of the 20th annual international conference on Supercomputing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Optimizing instruction-set extensible processors under data bandwidth constraints
Proceedings of the conference on Design, automation and test in Europe
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Amdahl's law revisited for single chip systems
International Journal of Parallel Programming
Increasing data-bandwidth to instruction-set extensions through register clustering
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 13th international symposium on Low power electronics and design
An architecture framework for an adaptive extensible processor
The Journal of Supercomputing
Instruction set extension exploration in multiple-issue architecture
Proceedings of the conference on Design, automation and test in Europe
ARISE Machines: Extending Processors with Hybrid Accelerators
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Software optimization for MPSoC: a mpeg-2 decoder case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Proceedings of the 6th ACM conference on Computing frontiers
A scalable synthesis methodology for application-specific processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Application Development Framework for ARISE Reconfigurable Processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Design of an application-specific instruction set processor for high-throughput and scalable FFT
Proceedings of the Conference on Design, Automation and Test in Europe
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
The Journal of Supercomputing
Automated generation of custom processor core from C code
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Extended Instruction Exploration for Multiple-Issue Architectures
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 0.00 |
An application-specific instruction-set processor (ASIP) is ideally suited for embedded applications that have demanding performance, size, and power requirements that cannot be satisfied by a general purpose processor. ASIPs also have time-to-market and programmability advantages when compared to custom ASICs. The AutoTIE system simplifies the creation of ASIPs by automatically enhancing a base processor with application specific instruction set architecture (ISA) extensions, including instructions, operations, and register files. The new instructions, operations, and register files are automatically recognized and exploited by the entire software tool chain, including the C/C++ compiler. Thus, taking advantage of the generated ASIP does not require any changes to the application or any assembly language coding. AutoTIE uses the C/C++ compiler to analyze an application, and based on the analysis generates thousands, or even millions, of possible ISA extensions for the application. AutoTIE then uses performance and hardware estimation techniques to combine the ISA extensions into a large number of potential ASIPs, and for a range of hardware costs, chooses the ASIP that provides the maximum performance improvement. For example, for an application performing a radix-4 FFT, AutoTIE considers over 34,000 potential sets of ISA extensions. For hardware costs ranging from 7800 gates to 128,000 gates, AutoTIE combines these extensions to form 31 ASIPs, which provide performance improvements ranging from a factor of 1.12 to a factor of 11.3 compared to a general-purpose processor.