Efficient retargetable code generation using bottom-up tree pattern matching
Computer Languages
BURG: fast optimal instruction selection and tree parsing
ACM SIGPLAN Notices
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Global Code Selection of Directed Acyclic Graphs
CC '94 Proceedings of the 5th International Conference on Compiler Construction
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
The mimola design system: Tools for the design of digital processors
DAC '84 Proceedings of the 21st Design Automation Conference
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Operation tables for scheduling in the presence of incomplete bypassing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Effective compiler generation by architecture description
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
The ArchC architecture description language and tools
International Journal of Parallel Programming
Towards Automation of Testing High-Level Security Properties
Proceeedings of the 22nd annual IFIP WG 11.3 working conference on Data and Applications Security
Precise simulation of interrupts using a rollback mechanism
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
Compiler backend generation for application specific instruction set processors
APLAS'11 Proceedings of the 9th Asian conference on Programming Languages and Systems
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With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific instruction-set processors (ASIPs) are used to fine-tune hardware platforms to the intended application, demanding the availability of retargetable components throughout thewhole tool chain. A very promising approach is to model the target architecture using a dedicated description language that is rich enough to generate hardware components and the required tool chain, e.g., assembler, linker, simulator, and compiler. In this work we present a new structural architecture description language (ADL) that is used to derive the architecture dependent components of a compiler backend - most notably an instruction selector based on tree pattern matching. We combine our backend with gcc, thereby opening up the way for a large number of readily available high level optimizations. Experimental results show that the automatically derived code generator is competitive in comparison to a handcrafted compiler backend.