Structured computer organization; (2nd ed.)
Structured computer organization; (2nd ed.)
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient retargetable code generation using bottom-up tree pattern matching
Computer Languages
Computer system architecture (3rd ed.)
Computer system architecture (3rd ed.)
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Symbolic modeling and evaluation of data paths
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Efficient code generation for in-house DSP-cores
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formalization and automatic derivation of code generators.
Formalization and automatic derivation of code generators.
A machine independent algorithm for code generation and its use in retargetable compilers.
A machine independent algorithm for code generation and its use in retargetable compilers.
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Scheduling and binding bounds for RT-level symbolic execution
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Media architecture: general purpose vs. multiple application-specific programmable processor
DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploring Hypermedia Processor Design Space
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Quick piping: a fast, high-level model for describing processor pipelines
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
An Empirical Study of Retargetable Compilers
PSI '02 Revised Papers from the 4th International Andrei Ershov Memorial Conference on Perspectives of System Informatics: Akademgorodok, Novosibirsk, Russia
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Effective compiler generation by architecture description
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Generic netlist representation for system and PE level design exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Processor Description Languages
Processor Description Languages
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Journal of Systems and Software
| Hi-index | 0.00 |
Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler RECORD does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits to study the HW/SW trade-off between processor architectures and program execution speed.