Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Graph based retargetable microcode compilation in the MIMOLA design system
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Code Generation for Embedded Processors
Code Generation for Embedded Processors
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Constrained software generation for hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Reducing the complexity of ILP formulations for synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Constructive Method for Exploiting Code Motion
ISSS '96 Proceedings of the 9th international symposium on System synthesis
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Abstract: DSP algorithms are, in most cases, subject to hard real-time constraints. In the case of programmable DSPs, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an integer programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side-effects.