Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing the complexity of ILP formulations for synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Statistical performance-driven module binding in high-level synthesis
Proceedings of the 11th international symposium on System synthesis
Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Cross-level hierarchical high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Multiple-Wordlength Resource Binding
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Design reuse through high-level library mapping
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Behavioural Bitwise Scheduling Based on Computational Effort Balancing
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An ILP Formulation for Reliability-Oriented High-Level Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Behavioral Synthesis Method with Special Functional Units
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified approach for scheduling and allocation
Integration, the VLSI Journal
Data path refinement algorithm in high-level synthesis based on dynamic programming
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Automated generation of custom processor core from C code
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
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