Optimum and heuristic synthesis of multiple word-length architectures

Authors:
George A. Constantinides;Peter Y. K. Cheung;Wayne Luk
Affiliations:
Department of Electrical and Electronic Engineering, Imperial College, London SW7 2BT, U.K.;Department of Electrical and Electronic Engineering, Imperial College, London SW7 2BT, U.K.;Department of Computing, Imperial College, London SW7 2BZ, U.K.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interaction between scheduling, allocation, and binding, are complicated by the existence of multiple word-length operators. Both optimum and heuristic approaches to the combined problem are formulated. The optimum solution involves modeling as an integer linear program, while the heuristic solution considers intertwined scheduling, binding, and resource word-length selection. Techniques are introduced to perform scheduling with incomplete word-length information, to combine binding and word-length selection, and to reline word-length information based on critical path analysis. Results are presented for several benchmark and artificial examples, demonstrating significant resource savings of up to 46% are possible by considering these problems within the proposed unified framework.