A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Accuracy Sensitive Word--Length Selection for Algorithm Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
Synthesis And Optimization Of DSP Algorithms
Synthesis And Optimization Of DSP Algorithms
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
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This paper presents an alternative approach for multiple word-length architecture synthesis and optimization. It is based on an iterative refinement process on operation grouping, word-length assignment and high-level synthesis. The focus is on the sub-problem of operation grouping before word-length assignment, and within iterations. Two algorithms are proposed and first results show the interest of the approach and invite for more investigations in iterative grouping procedures.