Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rapid prototyping of field programmable gate array-based discrete cosine transform approximations
EURASIP Journal on Applied Signal Processing
Optimum wordlength search using sensitivity information
EURASIP Journal on Applied Signal Processing
Design and implementation of numerical linear algebra algorithms on fixed point DSPs
EURASIP Journal on Advances in Signal Processing
Proceedings of the 45th annual Design Automation Conference
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
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In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers, and registers. This paper presents algorithmic level theory and optimization techniques to select distinct word lengths for each computation which meet the desired accuracy and minimize the design cost for the given performance constraints. The reduction in cost is possible by avoiding unnecessary bit-level computations that do not contribute significantly to the accuracy of the final results. Thus we have introduced a new optimization variable, computation accuracy, into data-path synthesis. Our results show on an average, a 30% reduction in functional-resource area using distinct word lengths as opposed to use of a single optimized word length for the entire algorithm.