Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Microelectronic circuits, 2nd ed.
Microelectronic circuits, 2nd ed.
Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Theoretical analysis of word-level switching activity in the presence of glitching and correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
Proceedings of the conference on Design, automation and test in Europe
FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
Randomized Algorithms: A System-Level, Poly-Time Analysis of Robust Computation
IEEE Transactions on Computers
Proceedings of the 40th annual Design Automation Conference
Accuracy Sensitive Word--Length Selection for Algorithm Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
Perturbation Analysis for Word-length Optimization
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Synthesis And Optimization Of DSP Algorithms
Synthesis And Optimization Of DSP Algorithms
Automated Least-Significant Bit Datapath Optimization for FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wordlength optimization for linear digital signal processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Design exploration of quadrature methods in option pricing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This article introduces an automatic design procedure for determining the sensitivity of outputs in a digital signal processing design to small errors introduced by rounding or truncation of internal variables. The proposed approach can be applied to both linear and nonlinear designs. By analyzing the resulting sensitivity values, the proposed procedure is able to determine an appropriate distinct word-length for each internal variable in a fixed-point hardware implementation. In addition, the power-optimizing capabilities of word-length optimization are studied. Application of the proposed procedure to adaptive filters and polynomial evaluation circuits realized in a Xilinx Virtex FPGA has resulted in area reductions of up to 80% (mean 66%) combined with power reductions of up to 98% (mean 87%) and speed-up of up to 36%(mean 20%) over common alternative design strategies.