Automating Customisation of Floating-Point Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Synthesis of saturation arithmetic architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An analytical approach for dynamic range estimation
Proceedings of the 41st annual Design Automation Conference
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
LNS architectures for embedded model predictive control processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
Dynamic range estimation for nonlinear systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Quality-driven design by bitwidth optimization for video applications
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Bitwidth-aware scheduling and binding in high-level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Optimum wordlength search using sensitivity information
EURASIP Journal on Applied Signal Processing
Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy
ACM Transactions on Embedded Computing Systems (TECS)
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Journal of Signal Processing Systems
A cyclic scheduling problem with an undetermined number of parallel identical processors
Computational Optimization and Applications
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
Proceedings of the International Conference on Computer-Aided Design
Multi-level customisation framework for curve based monte carlo financial simulations
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Optimising performance of quadrature methods with reduced precision
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Mathematical and Computer Modelling: An International Journal
High-level synthesis under fixed-point accuracy constraint
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software