IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
On lower bounds for scheduling problems in high-level synthesis
Proceedings of the 37th Annual Design Automation Conference
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
A system-level energy minimization approach using datapath width optimization
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
High-level synthesis of multiple-precision circuits independent of data-objects length
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
High Level Synthesis Of Multi-Precision Data Flow Graphs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Architecture and synthesis for multi-cycle on-chip communication
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
High-level synthesis under fixed-point accuracy constraint
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Speed and precision in range analysis
SBLP'12 Proceedings of the 16th Brazilian conference on Programming Languages
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Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifications without bitwidth analysis may introduce wasted resources. Furthermore, conventional high-level synthesis techniques usually focus on uniform-width resources, thus they cannot obtain the full resource savings even with bitwidth information. This work develops a bitwidth-aware synthesis flow, including bitwidth analysis, scheduling and binding, and register allocation and binding, to exploit the multi-bitwidth nature of operations and variables for area-efficient designs. We also develop lower bound estimation to evaluate the efficiency of our proposed solutions for register allocation and binding. The flow is implemented in the MCAS synthesis system [11]. Experimental results show that our proposed bitwidth-aware synthesis flow reduces area by 36% and wire-length by 52% on average compared to the uniform-width MCAS flow, while achieving the same performance.