Integer and combinatorial optimization
Integer and combinatorial optimization
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
Bitwidth-aware scheduling and binding in high-level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design exploration framework under impreciseness based on register-constrained inclusion scheduling
ASIAN'04 Proceedings of the 9th Asian Computing Science conference on Advances in Computer Science: dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday
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