Retiming synchronous circuitry with imprecise delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Register allocation for predicated code
Proceedings of the 28th annual international symposium on Microarchitecture
Stage scheduling: a technique to reduce the register requirements of a modulo schedule
Proceedings of the 28th annual international symposium on Microarchitecture
Heuristics for register-constrained software pipelining
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Lifetime-Sensitive Modulo Scheduling in a Production Environment
IEEE Transactions on Computers
Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Architectural synthesis with possibilistic programming
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
Design Space Exploration for Data Path Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fuzzy scheduling in compilers optimizations
ISUMA '95 Proceedings of the 3rd International Symposium on Uncertainty Modelling and Analysis
Register-Sensitive Software Pipelining
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Efficient design exploration based on module utility selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a design exploration framework which consider impreciseness in design specification. In high-level synthesis, imprecise information is often encountered. Two kinds of impreciseness are considered here: imprecise characteristics of functional units and imprecise design constraints. The proposed design exploration framework is based on efficient scheduling algorithm which considers impreciseness, Register-Constrained Inclusion Scheduling. We demonstrate the effectiveness of our framework by exploring a design solution for a well-known benchmark, Voltera filter. The selected solution meets the acceptability criteria while minimizing the total number of registers.