System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Instruction set mapping for performance optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis of optimal clocking schemes
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Reducing the complexity of ILP formulations for synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Improving the computational performance of ILP-based problems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Design exploration framework under impreciseness based on register-constrained inclusion scheduling
ASIAN'04 Proceedings of the 9th Asian Computing Science conference on Advances in Computer Science: dedicated to Jean-Louis Lassez on the Occasion of His 5th Cycle Birthday
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Abstract: This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3-dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to the 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: a careful selection of candidate clock lengths; and tight bounds on the number of functional units of each type or on the schedule length.