VLSI array processors
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Introduction to artificial neural systems
Introduction to artificial neural systems
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On optimal board-level routing for FPGA-based logic emulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High level VLSI synthesis for multichip designs
High level VLSI synthesis for multichip designs
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical behavioral partitioning for multicomponent synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
REMARC (abstract): reconfigurable multimedia array coprocessor
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Configuration cloning: exploiting regularity in dynamic DSP architectures
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Efficient resource arbitration in reconfigurable computing environments
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Communicating sequential processes
Communications of the ACM
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Digital Filters and Signal Processing
Digital Filters and Signal Processing
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Synthesis for Field-Programmable Gate Arrays
Logic Synthesis for Field-Programmable Gate Arrays
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
The Java environment for reconfigurable computing
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A 800 Mpixel/sec reconfigurable image correlator on XC6216
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
SLIF: a specification-level intermediate format for system design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
An Effective Design System for Dynamically Reconfigurable Architectures
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Emulating Large Designs on Small Reconfigurable Hardware
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Application Specific Macro Based Synthesis
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Partitioning for fpga-based reconfigurable computers
Partitioning for fpga-based reconfigurable computers
A methodology for control-dominated systems codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
A method for area estimation of data-path in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for minimizing and balancing I/O during functional partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The advent of reconfigurable logic arrays facilitates the development of adaptive architectures that have wide applicability as stand- alone intelligent systems. The hardware structure of such architectures can be rapidly altered to suit the changing computational needs of an application during its execution. The power of adaptive architectures has been demonstrated primarily in image processing, digital signal processing, and other areas such as neural networks and genetic algorithms. This chapter discusses the state-of-the-art architectures, their classification, and their applications. In order to effectively exploit adaptive architectures, efficient and retargetable design synthesis techniques are necessary. Further, the synthesis techniques must be fully integrated with design partitioning methods to make use of the multiplicity of reconfigurable devices provided by adaptive architectures. This chapter provides a description of a collection of synthesis and partitioning techniques and their embodiment in the SPARCS (Synthesis and Partitioning for Adaptive Reconfigurable Computing Systems) system.