A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Rapid implementation of a genetic sequence comparator using field-programmable logic arrays
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
The anyboard rapid prototyping environment
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Programmable active memories: a performance assessment
Proceedings of the 1993 symposium on Research on integrated systems
Spectral k-way ratio-cut partitioning and clustering
Proceedings of the 1993 symposium on Research on integrated systems
Efficient network flow based min-cut balanced partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
A fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs
DAC '94 Proceedings of the 31st annual Design Automation Conference
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A prototyping environment for hardware/software codesign in the COBRA project
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
SHARP-looking geometric partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We described the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.