Introduction to algorithms
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
A method for partitioning UNITY language in hardware and software
EURO-DAC '94 Proceedings of the conference on European design automation
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
SLIF: a specification-level intermediate format for system design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Comparison of Functional and Structural Partitioning
ISSS '96 Proceedings of the 9th international symposium on System synthesis
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Local ratio cut and set covering partitioning for huge logic emulation systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
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We improve upon a new approach for automatically partitioning a system among several FPGAs. The new approach partitions a system's functional specification, now commonly available, rather than its structural implementation. The improvement uses a bus, the FunctionBus, for implementing function calls among FPGA's, The bus can be used with any number of and its protocol uses only a small amount of existing FPGA hardware, requiring no special hardware. While functional rather than structural partitioning can substantially reduce the number of input/output pins using (I/O) the FunctionBus takes such reduction even further. In particular, performance and I/0can be traded-off by varying the bus size, as demonstrated using several examples.