A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Hardware/software partitioning and minimizing memory interface traffic
EURO-DAC '94 Proceedings of the conference on European design automation
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Computer-Aided Hardware-Software Codesign
IEEE Micro
System synthesis via hardware-software co-design
System synthesis via hardware-software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
An approach to the adaptation of estimated cost parameters in the COSYMA system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Port calling: a transformation for reducing I/O during multi-package functional partitioning
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
A path analysis based partitioning for time constrained embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
Integrating communication protocol selection with partitioning in hardware/software codesign
Proceedings of the 11th international symposium on System synthesis
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Codex-dp: co-design of communicating systems using dynamic programming
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware resource allocation for hardware/software partitioning in the LYCOS system
Proceedings of the conference on Design, automation and test in Europe
Partitioning sequential programs for CAD using a three-step approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ParTS: A Partitioning Transformation System
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Algorithm and architecture-level design space exploration using hierarchical data flows
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Procedure cloning: a transformation for improved system-level functional partitioning
EDTC '97 Proceedings of the 1997 European conference on Design and Test
The importance of interfaces: a HW/SW codesign case study
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Aspects of system modelling in Hardware/Software partitioning
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Low-complex dynamic programming algorithm for hardware/software partitioning
Information Processing Letters
Finding optimal hardware/software partitions
Formal Methods in System Design
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Low-complex dynamic programming algorithm for hardware/software partitioning
Information Processing Letters
Server-side coprocessor updating for mobile devices with FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Evaluation of data-parallel H.264 decoding approaches for strongly resource-restricted architectures
Multimedia Tools and Applications
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
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This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardware- and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n x n x A) and the space-complexity is O(n x A) where A is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software.