A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Design Space Exploration for Dynamically Reconfigurable Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Execution Environment for Reconfigurable Computing
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
A system-level approach to hardware reconfigurable systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System Level Design of Reconfigurable Systems-on-Chip
System Level Design of Reconfigurable Systems-on-Chip
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Calibration of abstract performance models for system-level design space exploration
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Run-time management of a MPSoC containing FPGA fabric tiles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
Dynamic coprocessor management for FPGA-enhanced compute platforms
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Software-Hardware Partitioning Strategy Using Hybrid Genetic and Tabu Search
CSSE '08 Proceedings of the 2008 International Conference on Computer Science and Software Engineering - Volume 04
Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures
Transactions on High-Performance Embedded Architectures and Compilers I
Fine- and Coarse-Grain Reconfigurable Computing
Fine- and Coarse-Grain Reconfigurable Computing
Evaluation of runtime task mapping heuristics with rSesame: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime Task Mapping Based on Hardware Configuration Reuse
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
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Performing runtime evaluation together with design time exploration enables a system to be more efficient in terms of various design constraints, such as performance, chip area, and power consumption. rSesame is a generic modeling and simulation framework, which can explore and evaluate reconfigurable systems at both design time and runtime. In this paper, we use the rSesame framework to perform a thorough evaluation (at design time and at runtime) of various task mapping heuristics from the state of the art. An extended Motion-JPEG (MJPEG) application is mapped, using the different heuristics, on a reconfigurable architecture, where different Field Programmable Gate Array (FPGA) resources and various nonfunctional design parameters, such as the execution time, the number of reconfigurations, the area usage, reusability efficiency, and other parameters, are taken into consideration. The experimental results suggest that such an extensive evaluation can provide a useful insight both into the characteristics of the reconfigurable architecture and on the efficiency of the task mapping.