Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Dynamic communication models in embedded system co-simulation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Proceedings of the 37th Annual Design Automation Conference
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Algorithmic transformation techniques for efficient exploration of alternative application instances
Proceedings of the tenth international symposium on Hardware/software codesign
An IDF-based trace transformation method for communication refinement
Proceedings of the 40th annual Design Automation Conference
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A software framework for efficient system-level performance evaluation of embedded systems
Proceedings of the 2003 ACM symposium on Applied computing
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Trace-driven HW/SW cosimulation using virtual synchronization technique
Proceedings of the 42nd annual Design Automation Conference
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Multi-processor system design with ESPAM
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A Mixed-level Co-simulation Method for System-level Design Space Exploration
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
Evaluating the model accuracy in automated design space exploration
Microprocessors & Microsystems
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A high abstraction, high accuracy power estimation model for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
RETHROTTLE: execution throttling in the REDEFINE SoC architecture
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Generation and calibration of compositional performance analysis models for multi-processor systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A High-level Microprocessor Power Modeling Technique Based on Event Signatures
Journal of Signal Processing Systems
Automatic performance model synthesis from hardware verification models
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
Proceedings of the 24th symposium on Integrated circuits and systems design
ACM Transactions on Embedded Computing Systems (TECS)
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Calibration of deployment simulation models: a multi-paradigm modelling approach
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
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High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.