Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework

Authors:
Luciano Ost;Marcelo Mandelli;Gabriel Marchesan Almeida;Leandro Soares Indrusiak;Leandro Moller;Manfred Glesner;Gilles Sassatelli;Michel Robert;Fernando Moraes
Affiliations:
LIRMM, Montpellier, France;PUCRS, Porto Alegre, Brazil;LIRMM, Montpellier, France;Department of Computer Science - University of York, York, England UK;FG MES - Technische Universität Darmstadt, Darmstadt, Germany;FG MES - Technische Universität Darmstadt, Darmstadt, Germany;LIRMM, Montpellier, France;LIRMM, Montpellier, France;PUCRS, Porto Alegre, Brazil
Venue:
Proceedings of the 24th symposium on Integrated circuits and systems design
Year:
2011

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Abstract

The power evaluation of NoC-based MPSoCs is an important and a time-consuming process. Mapping tasks onto processing elements (PEs) has a critical impact on system performance, as well as power dissipation. To cope with complex dynamic behavior of applications, it is common to perform task mapping at runtime so that the utilization of processors and interconnect can be taken into account when deciding the most appropriate PE to host tasks. On the other hand, the process of accurately comparing different mapping heuristics can be very costly once each adopted solution has to be evaluated using simulation that can take hours or even days in the case of large MPSoCs. In this context, this paper has two major contributions: (i) evaluation of dynamic mapping by employing a model-based framework that unifies abstract models of applications, NoC-based platforms and mapping heuristics, and (ii) power consumption evaluation of such heuristics by using a rate-based power model.