Proceedings of the 6th international workshop on Hardware/software codesign
Algorithms and Tools for Network on Chip Based System Design
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Proceedings of the 42nd annual Design Automation Conference
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Automated memory-aware application distribution for Multi-processor System-on-Chips
Journal of Systems Architecture: the EUROMICRO Journal
A contextual resources use: a proof of concept through the APACHES' platform
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time management of a MPSoC containing FPGA fabric tiles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Dynamic task allocation strategies in MPSoC for soft real-time applications
Proceedings of the conference on Design, automation and test in Europe
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A decentralised task mapping approach for homogeneous multiprocessor network-on-chips
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
Proceedings of the 24th symposium on Integrated circuits and systems design
Multi-task dynamic mapping onto NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Utility accrual object distribution in MPSoC real-time embedded systems
Journal of Computer and System Sciences
Hybrid interconnect design for heterogeneous hardware accelerators
Proceedings of the Conference on Design, Automation and Test in Europe
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Early exploration for platform architecture instantiation with multi-mode application partitioning
Proceedings of the 50th Annual Design Automation Conference
CADSE: communication aware design space exploration for efficient run-time MPSoC management
Frontiers of Computer Science: Selected Publications from Chinese Universities
Journal of Systems Architecture: the EUROMICRO Journal
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Communication and migration energy aware task mapping for reliable multiprocessor systems
Future Generation Computer Systems
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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Efficient run-time mapping of tasks onto Multiprocessor System-on-Chip (MPSoC) is very challenging especially when new tasks of other applications are also required to be supported at run-time. In this paper, we present a number of communication-aware run-time mapping heuristics for the efficient mapping of multiple applications onto an MPSoC platform in which more than one task can be supported by each processing element (PE). The proposed mapping heuristics examine the available resources prior to recommending the adjacent communicating tasks on to the same PE. In addition, the proposed heuristics give priority to the tasks of an application in close proximity so as to further minimize the communication overhead. Our investigations show that the proposed heuristics are capable of alleviating Network-on-Chip (NoC) congestion bottlenecks when compared to existing alternatives. We map tasks of applications onto an 8x8 NoC-based MPSoC to show that our mapping heuristics consistently leads to reduction in the total execution time, energy consumption, average channel load and latency. In particular, we show that energy savings can be up to 44% and average channel load is improved by 10% for some cases.