Hybrid interconnect design for heterogeneous hardware accelerators

Authors:
Cuong Pham-Quoc;Jan Heisswolf;Stephan Werner;Zaid Al-Ars;Jürgen Becker;Koen Bertels
Affiliations:
Delft University of Technology, Netherlands;Karlsruhe Institute of Technology, Germany;Karlsruhe Institute of Technology, Germany;Delft University of Technology, Netherlands;Karlsruhe Institute of Technology, Germany;Delft University of Technology, Netherlands
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories. A good interconnect design plays a key role in improving the performance of such systems. In this paper, we introduce a hybrid communication infrastructure using both the standard bus and our area-efficient and delay-optimized network on chip for heterogeneous multicore systems, especially hardware accelerator systems. An adaptive data communication-based mapping for reconfigurable hardware accelerators is proposed to obtain a low overhead and latency interconnect. Experimental results show that the proposed communication infrastructure and the adaptive data communication-based mapping achieves a speed-up of 2.4× with respect to a similar system using only a bus as interconnect. Moreover, our proposed system achieves a reduction of energy consumption of 56% compared to the original system.