Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
RASoC: A Router Soft-Core for Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-Chip
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
NoC-Based FPGA: Architecture and Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Multicasting based topology generation and core mapping for a power efficient networks-on-chip
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip
Proceedings of the Annual FPGA Conference
Hybrid interconnect design for heterogeneous hardware accelerators
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
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Present day technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. The latest FPGAs can support only about 10 million gates to accomodate all logic and the associated routing. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This ensures that the maximum area can be utilized by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. In this paper, we implement a parallel router which can support five simultaneous routing requests at the same time with an area overhead of only 352 Xilinx Virtex-II Pro FPGA slices (2. 57% of XC2VP30). We introduce optimizations in XY routing and decoding logic thereby gaining in area and performance. The header overhead is 8 bits per packet and the packet size can vary between 16 and 128 bits. We also implement a 3 x 3 mesh network with a total area overhead of 28% leaving 72% of the area available for the logic in a Virtex-II Pro XC2VP30 device. We characterize the router and several mesh networks for power and performance parameters.