An evaluation of an integrated on-chip/off-chip network for high-performance reconfigurable computing

Authors:
Andrew G. Schmidt;William V. Kritikos;Shanyuan Gao;Ron Sass
Affiliations:
Information Sciences Institute, University of Southern California, Arlington, VA;Reconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, Charlotte, NC;Reconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, Charlotte, NC;Reconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, Charlotte, NC
Venue:
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Year:
2012

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Abstract

As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the highperformance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).